An Introduction to VHDL
for Synthesis and Simulation
David Pellerin, President, Accolade Design Automation, Inc.
Note: this is a preliminary version of an on-line introduction to VHDL
and VHDL-based design methods. Some of the information in this document is
incomplete, and some figures have yet to be included. Your comments on the
usefulness of this information are welcome and appreciated. Please send
comments to email@example.com
Also, be sure to check out
VHDL Made Easy
by David Pellerin
and Douglas Taylor (Prentice Hall, 1996). VHDL Made Easy is
over 400 pages of useful information for new and experienced VHDL
VHDL (VHSIC Hardware Description Language) is becoming
increasingly popular as a way to capture complex digital electronic
circuits for both simulation and synthesis. Digital circuits captured using
VHDL can be easily simulated, are more likely to be synthesizable into
multiple target technologies, and can be archived for later modification
In his introduction to A VHDL Primer (Prentice Hall, 1992),
Jayaram Bhasker writes, "VHDL is a large and complex language with
many complex constructs that have complex semantic meanings...". This
statement, with its possibly record-breaking three instances of the word
"complex", reflects a common and for the most part correct perception
it is a large and complicated language.
VHDL is a rich and powerful language. But is VHDL really so
hard to learn and use? VHDL is not impenetrable, if you follow
well-established coding conventions and borrow liberally from sample circuits
such as those found in this introduction.
Goals Of This Introduction
The intent of this work is to introduce VHDL to engineers who will be
using the language to describe circuits for implementation in
programmable logic or ASICs. To this end, we will avoid prolonged
discussions that are appropriate only for developers of simulation models
and system-level simulations, and concentrate instead on those aspects of
the language that are most useful for circuit synthesis. We will give you
enough information to quickly get started using VHDL, and will suggest
coding styles that are appropriate using a wide variety of available
synthesis and simulation tools.
Along the way, we'll be examining the many advantages of using
VHDL for synthesis and simulation, and we will also explore some of the
drawbacks of using VHDL when compared to alternative design capture
methods. We'll see how VHDL fits into the overall electronic design
process, and will focus closely on the design process as it relates to
FPGA, PLD and ASIC design problems.
This Introduction to VHDL is derived from a 4-hour seminar on VHDL synthesis and
simulation. This is not a sales
pitch, but instead provides valuable, detailed information for those considering
VHDL (or other hardware description languages) as a design alternative. The introduction to VHDL will provide you with the
information you need to begin making effective use of the language for electronic
What Is VHDL?
VHDL is a programming language that has been designed and optimized
for describing the behavior of digital circuits and systems. As
such, VHDL combines features of the following:
A Simulation Modeling Language
VHDL has many features appropriate for describing (to an excruciating
level of detail) the behavior of electronic components ranging from
simple logic gates to complete microprocessors and custom chips.
Features of VHDL allow electrical aspects of circuit behavior (such as
rise and fall times of signals, delays through gates, and functional
operation) to be precisely described. The resulting VHDL simulation
models can then be used as building blocks in larger circuits (using
schematics, block diagrams or system-level VHDL descriptions) for the
purpose of simulation.
A Design Entry Language
Just as high-level programming languages allow complex design concepts
to be expressed as computer programs, VHDL allows the behavior of
complex electronic circuits to be captured into a design system for
automatic circuit synthesis or for system simulation. Like Pascal, C and
C++, VHDL includes features useful for structured design techniques,
and offers a rich set of control and data representation features. Unlike
these other programming languages, VHDL provides features allowing
concurrent events to be described. This is important because the hardware
being described using VHDL is inherently concurrent in its operation.
Users of PLD programming languages such as PALASM, ABEL, CUPL
and others will find the concurrent features of VHDL quite familiar.
Those who have only programmed using software programming
languages will, however, have some new concepts to grasp.
A Test Language
One of the most important (and under-utilized) aspects of VHDL is its
ability to capture the performance specification for a circuit, in a form
commonly refered to as a test bench. Test benches are VHDL
descriptions of circuit stimulus and corresponding expected outputs that
verify the behavior of a circuit over time. Test benches should be an
integral part of any VHDL project, and should be created in parallel with
other descriptions of the circuit.
A Netlist Language
VHDL is a powerful language with which to enter new designs at a high
level, but it is also useful as a low-level form of communication between
different tools in a computer-based design environment. VHDL's
structural language features allow it to be effectively used as a netlist
language, replacing (or augmenting) other netlist languages such as EDIF.
A Standard Language
One of the most compeling reasons for you to become experienced with
and knowledgable in VHDL is its adoptance as a standard in the
electronic design community. Using a standard language such as VHDL
will virtually guarantee that you will not have to throw away and re-
capture design concepts simply because the design entry method you
have chosen is not supported in a newer generation of design tools. Using
a standard language also means that you are more likely to be able to take
advantage of the most up-to-date design tools, and will have access to a
knowledge-base of thousands of other engineers, many of who are
solving problems similar to your own.
VHDL: As Simple or Complex as You Want It To Be
While it is true that VHDL is a large and complex language, it is not
actually difficult to get started with. Use it as you need it, and explore
advanced features as you become more confident. It won't take long
before you are coding with the masters!
A Brief History Of VHDL
VHDL (which stands for VHSIC Hardware Description Language) was
developed in the early 1980s as a spin-off of a high-speed integrated
circuit research project funded by the U.S. Department of Defense.
During the VHSIC program, researchers were confronted with the
daunting task of describing circuits of enormous scale (for their time) and
of managing very large circuit design problems that involved multiple
teams of engineers. With only gate-level design tools available, it soon
became clear that better, more structured design methods and tools would
need to be developed.
To meet this challenge, a team of engineers from three
companies -- IBM, Texas Instruments and Intermetrics -- were contracted
by the Department of Defense to complete the specification and
implementation of a new, language-based design description method. The
first publicly available version of VHDL, version 7.2, was made available
IEEE Standard 1076-1987
In 1986, the IEEE was presented with a proposal to standardize
the language, which it did in 1987 after substantial enhancements and
modifications were made by a team of commercial, government and
academic representatives. The resulting standard, IEEE 1076-1987, is the
basis for virtually every simulation and synthesis product sold today. An
enhanced and updated version of the language, IEEE 1076-1993, was
released in 1994, and VHDL tool vendors have been responding by
adding these new language features to their products.
IEEE Standard 1164
Although IEEE standard 1076 defines the complete VHDL language,
there are aspects of the language that make it difficult to write completely
portable design descriptions (descriptions that can be simulated
identically using different vendors' tools). The problems stems from the
fact that VHDL supports many abstract data types,
but does not directly address
the problem of characterizing different signal strengths or
commonly used simulation conditions such as unknowns and high-
impedence. Soon after IEEE 1076-1987 was adopted, simulator
companies began enhancing VHDL with new signal types (typically
through the use of syntactically legal, but non-standard enumerated types)
to allow their customers to accurately simulate complex electronic
circuits. This causes problems because design descriptions entered using
one simulator were often incompatible with other simulation
environments. VHDL was quickly becoming a non-standard.
To get around this problem of non-standard data types, another
standard was developed by commitee and adopted by the
IEEE. This standard, numbered 1164,
defines a standard package (a VHDL feature that allows commonly used
declarations to he collected into an external library) containing
definitions for a standard nine-valued data type. This standard data type is
called standard logic, and the IEEE 1164 package is often referred to as the
standard logic package, or sometimes MVL9 (for mutivalued logic, nine values).
The IEEE 1076-1987 and IEEE 1164 standards together form the
complete VHDL standard in widest use today. (IEEE 1076-1993 is
slowly working its way into the VHDL mainstream, but does not add
significant new features for synthesis users.)
The VITAL initiative (VHDL Initiative Toward ASIC Libraries) is an
effort to enhance VHDL's abilities for modeling timing in ASIC and
FPGA design environments. VITAL borrows liberally from existing
methods for timing annotation used in Verilog HDL. Specifically, the
VITAL standard (standard 1076.4, which as of this writing is in balloting
phase) describes a method for annotating delay information using the
same underlying tabular format as specified in Verilog. The adoptance of
this standard will make it much easier for ASIC and FPGA vendors to
create timing-annotated netlists and other data describing the detailed
behavior of their devices.
How Is VHDL Used?
VHDL is a general-purpose programming language optimized for
electronic circuit design. As such, there are many points in the overall
design process at which VHDL can help.
For design specification
VHDL can be used right up front, while you are still designing at a high
level, to capture the performance and interface requirements of each
component in a large system. This is particularly useful for large projects
involving many team members. Using a top-down approach to design, a
system designer may define the interface to each component in the
system, and describe the acceptance requirements of those components in
the form of a high-level test bench. The interface definition (typically
expressed as a VHDL entity declaration) and high-level performance
specification (the test bench) can then be passed on to other team
members for completion or refinement.
For design capture
Design capture is that phase in which the details of the system are entered
(captured) in a computer-based design system. In this phase, you may
express your design (or portions of your design) as schematics (either
board-level or purely functional) or using VHDL descriptions. If you are
going to be using synthesis technology, then you will want to write the
VHDL portions of the design using a style of VHDL that is appropriate
The design capture phase may include tools and design entry
methods other than VHDL. In many cases, design descriptions written in
VHDL are combined with other representations, such as schematics, to
form the complete system.
For design simulation
Once entered into a computer-based design system, you will probably
want to simulate the operation of your circuit to find out if it will meet the
functional and timing requirements developed during the specification
process. If you have created one or more test benches as a part of your
design specification, then you will use a simulator to apply the test bench
to your design as it is written for synthesis (a functional simulation) and
possibly using the post-synthesis version of the design as well.
For design documentation
The structured programming features of VHDL, coupled with its
configuration management features, make VHDL a natural form in which
to document a large and complex circuit. The value of using a
high-level language such as VHDL for design documentation is pointed out by
the fact that the U.S. Department of Defense now requires VHDL as the
standard format for communicating design requirements between
As an alternative to schematics
Schematics have long been a part of electronic system design, and it is
unlikely that they will become extinct anytime soon. Schematics have
their advantages, particularly when used to depict circuitry in block
diagram form. For this reason many VHDL design tools now offer th
ability to combine schematic and VHDL representations in a design.
As an alternative to proprietary languages
If you have used programmable logic devices in the past, then you have
probably already used some form of hardware description language
(HDL). Proprietary languages such as PALASM, ABEL, CUPL and
Altera's AHDL have been developed over the years by PLD device
vendors and design tool suppliers, and remain in widespread use today. In
fact, there are probably more users of PLD-oriented proprietary
languages in the word today than all other HDLs (including Verilog and
The FPGA/ASIC Design Process
The following diagram shows a simplified design process including both
synthesis and simulation, assuming that the target of the process is one or
more programmable logic or ASIC chips. The key to understanding this
process, and to understanding how best to use VHDL, is to remember the
importance of test development. Test development should begin as soon
as the general requirements of the system are known.
Where does VHDL fit in this diagram? VHDL (along with other forms of
entry, such as schematics and block diagrams), will be used for design
entry: after being captured into a design entry system using a text editor
(or via a design entry tool that generates VHDL from higher-level
graphical representations), the VHDL source code can be input to
simulation, allowing it to be functionally verified, or can be passed
directly to synthesis tools for implementation in a specified type of
On the test development side, VHDL test benches can be created
that exercise the circuit to verify that it meets the functional and timing
constraints of the specification. These test benches may be entered using
a text editor, or may be generated from other forms of test stimulus
information, such as graphical waveforms.
For accurate timing simulation of post-route circuits, you will
probably use a timing model generation program obtained from a device
vendor or third party simulation model supplier. Model generation tools
such as this typically generate timing-annotated VHDL source files that
support very accurate system-level simulation.
Why Should You Use VHDL?
Why choose to use VHDL for your design efforts? There are many likely
reasons; if you ask most VHDL tool vendors this question, the first
answer you will get is, "It will dramatically improve your productivity."
But just what does this mean? Can you really expect to get your projects
done faster using VHDL than using your existing design methods? The
answer is yes, but probably not the first time you use it, and only if you
apply VHDL is a structured manner. VHDL, like any high-level design
language, is of most benefit when you use a structured, top-down
approach to design. Real increases in productivity will come later, when
you have climbed higher on the VHDL learning curve and have
accumulated a library of re-usable VHDL components. Productivity
increases will also occur when you begin to use VHDL to enhance
communication between team members, and take advantage of the more
powerful tools for simulation and design verification that are available.
How will VHDL increase your productivity? By making it easy to
build and use libraries of commonly-used VHDL modules, VHDL makes
design reuse feel natural. As you discover the benefits of reusable code,
you will soon find yourself thinking of ways to write your VHDL
statements in ways that will make them general-purpose; writing portable
code will become an automatic reflex.
Another important reason to use VHDL, and another way that your
productivity can be improved (or destroyed, if you are not careful), is the
rapid pace of development in electronic design automation (EDA) tools
and in target technologies. Using a standard language such as VHDL can
greatly improve your chances of moving into more advanced tools
without having to re-enter your circuit descriptions. Your ability to
retarget circuits to new types of device targets will also be improved by
using a standard design entry method.
Why Should You Not Use VHDL?
To be fair, let's examine some of the most common reasons why you
might not want to use VHDL as your primary method of design entry.
Steep learning curve?
As described previously, there is a popular (and to some extent deserved)
perception that VHDL is hard to learn and use. While it is true that
VHDL is a big and complex language, there is certainly no need to learn
all of its features before beginning with your first few designs. Many of
the advanced (and obscure) features of VHDL are useful only for
simulation modeling, or are intended for advanced configuration
management. These parts of the language are rarely used when you are
designing for synthesis. If you stick with well-established coding
conventions, then you should have little trouble getting started. As you
gain confidence and experience in the language, you will naturally begin
to explore some of the more advanced features.
Scarcity of low-cost tools?
VHDL related design tools have historically carried a higher price tag
than other alternatives, due in part to the fact that most of these tools were
only available as smaller parts of large, workstation-based EDA tools.
More recently, however, lower cost simulation and synthesis tools have
appeared that make VHDL tools more competitive. FPGA vendors are
now offering low-cost, but powerful synthesis tools optimized for their
devices, and lower-cost simulation packages are also beginning to appear.
Lack of technology-specific features?
One of VHDL's major strengths, its general-purpose design, is also one of
its primary weaknesses when compared to other existing tools, most
notably PLD and FPGA design tools. While a PLD language such as
PALASM, ABEL or CUPL provides specialized language features for
accessing common device features (such as flip-flops and I/O buffers)
and for specifying physical data such as pin numbers, VHDL provides no
such features. This means that synthesis tool developers must publish
conventions (such as special attributes, comment fields or VHDL coding
standards) to allow their users to pass such information into the synthesis
tool. These conventions are rarely common between different tools, so
users are faced with a choice: either write completely technology-
independent VHDL code that may not be appropriate for the target device
or technology, or write VHDL code that is specific to a particular
This problem is actually not as bad as it sounds; the conventions
published and used by VHDL synthesis vendors are designed in such a
way that their use does not conflict with the use of similar features in
alternative tools. Special attributes for pin numbers, for example, will be
ignored by tools that do not have those attributes defined. Most probably,
if you will be writing VHDL source code that is intended for use with
more than one synthesis tool, then you will use VHDL's design
management and modularity features to isolate the technology-specific
statements to easily-modified sections of your design.
Lack of VHDL applications expertise?
If you have made extensive use of PLDs and FPGAs, you may have
become used to calling your local device vendor representative for help
and advice. PLD and FPGA applications engineers generally possess
craniums full of useful knowledge about PLD and FPGA applications,
and are often well versed in the use of PLD and FPGA tools.
Unfortunately, these same application engineers may not be completely
familiar with VHDL, and are probably not experts in using VHDL for
PLD and FPGA applications. This situation is changing, however, as
PLD and FPGA vendors adopt VHDL as a standard design entry method
for their devices.
What About Verilog?
When it comes to hardware description languages, VHDL is not the only
game in town. Verilog HDL has been around for many years as well, and
has a large number of fans who use it for both simulation and synthesis.
How does Verilog differ from VHDL? First, Verilog has some
advantage in availability of simulation models. Soon after its introduction
(by Gateway Design Automation in the mid 1980s), Verilog
established itself as the de facto standard language for ASIC simulation
libraries. The widespread popularity of Verilog HDL for this purpose has
left VHDL somewhat behind in support for a wide range of ASIC
devices. The VITAL initiative enhances VHDL with a standard method
of delay annotation that is similar to that used in Verilog. VITAL will
make it easier for ASIC vendors and others to quickly create VHDL
models from existing Verilog libraries.
Another feature that is defined in Verilog (in the Open Verilog
International published standard) is a programming language interface, or
PLI. The PLI makes it possible for simulation model writers to go outside
of Verilog when necessary to create faster simulation models, or to create
functions (using the C language) that would be difficult or inefficient to
implement directly in Verilog.
In VHDL's favor are its adoptance as an IEEE standard (standard
1076) and its higher-level design management features. These design
management features, which include the configuration declaration and
VHDL's library features, make VHDL an ideal language for large project
In most respects, however, VHDL and Verilog are identical in
function. The syntax is different (with Verilog looking very much like C,
and VHDL looking more like Pascal or Ada), but basic concepts are the
same. Both languages are easy to learn, but hard to master. Once you
have learned one of these languages, you will have no trouble
transitioning to the other.
The bottom line is this: arguing about language features is
pointless, and best left to late night sessions at the local tavern. You
should choose a set of tools to help you do your job. Select these tools
based on their features and their support for your specific application and
technology. Don't choose a hardware description language based only on
how it looks.
What About PLD Languages?
Many new users of VHDL have previous experience with simpler
PLD-oriented languages such as PALASM, ABEL or CUPL. How do these
languages differ from VHDL? The most important thing to keep in mind
about VHDL and these simpler languages is that VHDL was developed
primarily as a general-purpose simulation modeling language, while PLD
languages were developed as specialized languages for capture and
synthesis of relatively small digital circuits.
PLD languages, because of their modest roots, are generally quite
simple in the feature sets and easy to master. They include features (such
as built-in register primitives, pin numbering and output polarity controls)
that are specific to the PLD and FPGA devices that they are intended to
support. Because these languages have been designed specifically for
synthesis, they do not include features (such as delay specifiers) that are
Perhaps just as important as the general features of PLD and FPGA
design languages is their low cost: many of these tools are actually
available free from vendors of PLDs and FPGA, or are sold at prices far
below what you would expect to pay for VHDL or Verilog based
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